Synopsys, Inc. today announced the availability of its Verification IP (VIP) and source code test suite for ARM AMBA 5 Coherent Hub Interface (CHI) Issue B. Synopsys VC VIP for AMBA CHI has been widely adopted by SoC leaders for successful verification closure and tape out of coherent subsystems and interconnects. Synopsys VIP for the latest AMBA CHI Issue B specification enables customers and partners to extend the standard architecture for their next-generation coherent designs with new enhancements for increased performance.
"Coherent systems are being adopted rapidly in a wide range of applications to scale performance with multiple processor clusters or I/O coherent accelerators and I/O," said Andy Nightingale, vice president of marketing, systems IP, Systems and Software Group, ARM. "Collaborating on AMBA CHI Issue B VIP with our ecosystem partner, Synopsys, enables SoC teams to verify complex coherency-based designs with ease of use, and to increase productivity and performance for accelerated verification closure."
Synopsys next-generation VIP provides performance metrics for latency and throughput analysis, a configurable interconnect model, a reference verification platform and system-level checks for protocol, data integrity and cache coherency. The VIP is natively integrated with Synopsys' Verdi® Protocol Analyzer debug solution. Built-in coverage and verification plans are also included to speed up verification coverage closure.
"Our Verification IP and interface IP solutions for ARM's interconnect technology build on more than a decade-long collaboration for development of the latest AMBA protocol," said Vikas Gautam, group director of VIP R&D and corporate applications in the Verification Group at Synopsys. "Our ongoing partnership with ARM continues to enable designers to create their next-generation server and networking devices with the latest AMBA CHI technology."